Cypress Semiconductor /psoc63 /DW0 /CH_STRUCT[6] /INTR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INTR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH)CH

Description

Interrupt

Fields

CH

Set to ‘1’, when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with ‘1’, to clear bit. Write INTR_SET.CH field with ‘1’, to set bit.

Links

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